1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a multilayer semiconductor device incorporating an electrical fuse with a fuse window defined in a superjacent insulating layer to allow access with relatively thin insulation therethrough, in which a generally ring-shaped guard ring surrounds the fuse and its adjacent area to prevent contaminants from entering internal circuitry through the fuse window.
2. Discussion of the Background
Electrical fuses are employed in various semiconductor devices to provide redundant circuits and programmable memory, as well as adjustable resistance for setting up a desired voltage. One particular type of electrical fuse is a silicon fuse formed of a patterned layer of polysilicon deposited over a semiconductor substrate on which an integrated circuit (IC) is constructed. As an IC chip typically has a multilayered structure wherein various components and wires are layered one atop another with one or more layers of insulating material interposed therebetween, a silicon fuse has a window defined in its superjacent insulating layers to allow blowing or cutting off of the fuse, for example, through laser irradiation, during configuration of the semiconductor device.
One problem encountered by such an electrical fuse is that the fuse window allows moisture and other contaminants to enter into the insulation layers, which are relatively permeable to water, to reach wiring and circuit components inside the multilayered structure. Not surprisingly, this affects characteristics and performance of the internal circuitry and eventually reduces reliability of the IC chip.
To address this problem, a typical approach is to provide a generally ring-shaped guard ring of impervious material that surrounds the fuse and fuse window to prevent penetration of foreign matter into the internal circuitry.
FIG. 1 is a plan view schematically illustrating a conventional semiconductor device 101, shown with several components omitted for clarity, and FIGS. 2 and 3 are cross-sectional views of the semiconductor device 101 taken along lines X-X′ and Y-Y′, respectively, of FIG. 1.
As shown in FIGS. 1 through 3, the semiconductor device 101 is built on a substrate 102 of semiconductor material covered by a base insulating layer 103 for insulation.
On the base insulating layer 103 are a fuse or fusible link 105 with a pair of wires 107 each extending from one end of the fuse 105, as well as a generally ring-shaped guard ring 109 surrounding the fuse 105 and its adjacent area, all formed of silicon deposited and patterned over the base insulating layer 103. The silicon guard ring 109 is partially open with a pair of notches 109a cut in one side thereof to allow the wires 107 to extend from inside to outside the guard ring 109 without contacting, hence in electrical isolation from, the guard ring 109.
On the base insulating layer 103, a first interlayer insulating layer 111 covers the surfaces of the fuse 105 and the wires 107 as well as the surfaces of the guard ring 109 for electrically isolating the silicon layers from metal wiring.
The first interlayer insulating layer 111 has a contact hole defined above and along the silicon guard ring 109, which is filled with metal to form a generally ring-shaped first via guard ring 113 within the interlayer insulating layer 111 which surrounds, in plan view, the silicon fuse 105 and its adjacent area. Similar to the silicon guard ring 109, the first via guard ring 113 is partially open above the pair of notches 109a cut on one side of the subjacent guard ring 109 to allow the wires 107 to extend from inside to outside the guard ring 113 without contacting, hence in electrical isolation from, the guard ring 113.
Above the first interlayer insulating layer 111 is a generally rectangular ring-shaped, closed first metal guard ring 115 formed of metal deposited above and along the first via guard ring 111, which surrounds, in plan view, the silicon fuse 105 and its adjacent area.
Disposed on the first interlayer insulating layer 111 is a second interlayer insulating layer 117 for electrically isolating metal wires from each other, which covers the surfaces of the first metal guard ring 115. The second interlayer insulating layer 117 has a via hole defined above and along the first metal guard ring 115, which is filled with metal to form a generally rectangular ring-shaped, closed second via guard ring 119 within the second interlayer insulating layer 117, which surrounds, in plan view, the silicon fuse 105 and its adjacent area.
Above the second interlayer insulating layer 117 is a generally rectangular ring-shaped, closed second metal guard ring 121 formed of metal deposited on and along the second via guard ring 119, which surrounds, in plan view, the silicon fuse 105 and its adjacent area.
Finally, the semiconductor device 101 is topped by a final passivation or insulating layer 123 disposed on the second interlayer insulating layer 117 to cover the surfaces of the second metal guard ring 121.
The semiconductor device 101 has a fuse window 125 defined in the insulating layers 111, 117, and 123, wherein either no insulating layer or an insulating layer thinner than that at the other portions is disposed above the silicon fuse 105 to provide access to the silicon fuse 105 with relatively thin insulation therethrough. The layered guard rings 109, 113, 115, 119, and 121 surrounding the fuse 105, and hence surrounding the fuse window 125 disposed thereabove as well, serve to prevent atmospheric moisture and other contaminants from penetrating into the permeable insulating layers through the fuse window 125, and eventually into the internal circuitry.
Although providing substantially greater protection against contamination than a configuration without guard rings, the semiconductor device 101 with the multilayered guard rings still has a risk of leaking foreign matter into the internal circuitry. As mentioned, the conventional device 101 has the guard rings 109 and 113, immediately adjacent to the silicon wires 107, partially open to allow the wires 107 to extend outward from the fuse 105 in electrical isolation from the guard rings. Unfortunately, this partial opening leaves a path for contaminants to break through the guard rings to reach the internal circuitry, making the conventional semiconductor device 101 less reliable than would otherwise be expected.